This application contains subject matter which is related to copending U.S. patent application Ser. No. 08/616,913 entitled A METHOD OF MEASURING RETENTION PERFORMANCE AND IMPRINT DEGRADATION OF FERROELECTRIC FILMS filed on the same date as this application entitled "A Method of Measuring Retention Performance and Imprint Degradation of Ferroelectric Films", which is incorporated herein by this reference.
This invention relates generally to ferroelectric films. More particularly, the present invention relates to doping lead zirconate titantate ("PZT") ferroelectric films with either strontium or calcium, or a combination thereof, and by controlling the lead composition of the PZT film, in a manner that improves data retention performance in a ferroelectric capacitor, and in a corresponding ferroelectric memory.
Within film grain boundaries, PZT crystallizes in the perovskite structure shown in FIG. 1. Unit cell 10 is a simple cubic unit with a large cation 12 on the corners of the unit cell, a smaller cation 16 in the body center of the unit cell, and oxygen anions 14 in the centers of the unit cell faces. Each large cation 12 occupies a designated "A site" in unit cell 10, which, in PZT, is lead (Pb). The small cation 16 occupies the designated "B site" in unit cell 10, which, in PZT, is either zirconium (Zr) or titanium (Ti). Each oxygen anion 14 occupies a designated "O site" in unit cell 10. The perovskite structure is a network of corner-linked oxygen octahedra, with the smaller cation 16 filling the octahedral holes and the large cation 12 filling the dodecahedral holes.
The unit cell 10 shown in FIG. 1 is not a perfect cube, but is slightly distorted, with the small cation 16 occupying one of two stable positions within the unit cell. Since the small cation 16 is not exactly in the center of the unit cell 10, the perovskite crystal has an associated spontaneous electric dipole. PZT is ferroelectric in that the direction of the electric dipole can be reversed by the temporary application of an external electric field. The direction of the electric dipole remains until an opposite electric field is applied.
Referring now to FIGS. 2A and 2B, a ferroelectric capacitor 18 is shown, wherein the dielectric material of the capacitor is formed of PZT or other ferroelectric materials. A corresponding hysteresis loop 20 is shown that is a measure of the ferroelectric polarization of ferroelectric capacitor 18. The applied external electric field is represented along the x-axis, and the resultant charge or polarization is represented along the y-axis. Once an externally applied electric field exceeds a material-specific "coercive voltage" (V.sub.C), ferroelectric capacitor 18 begins to polarize. If the applied electric field is increased, the ferroelectric material in capacitor 18 becomes fully polarized or "saturated", wherein the polarization vector of most of the grains in the material are aligned in the same direction. Once the external electric field is removed, a remanent polarization represented by point Q.sub.2 remains. If the electric field is reversed in polarity and exceeds the coercive voltage (-V.sub.C) in the opposite direction, ferroelectric capacitor 18 begins to polarize in the opposite direction. If the applied electric field is increased, the ferroelectric material in capacitor 18 saturates in the opposite direction. Once the external electric field is removed, a remanent polarization represented by point Q.sub.1 remains. The remanent polarization of "stable states" Q.sub.1 and Q.sub.2 of ferroelectric capacitor 18 can be toggled by application of two opposite external voltages exceeding the coercive voltage.
Referring now to FIG. 3, an integrated ferroelectric memory cell 22 includes two ferroelectric capacitors 48A and 48B, as well as two field-effect transistors ("FETs") 46A and 46B. More specifically, ferroelectric memory cell 22 is actually the combination of two one-transistor, one-capacitor ("1T-1C") memory cells sharing a common bit line contact. Memory cell 22 includes a substrate or epitaxial layer 24, a thick field oxide layer 26 for isolating transistors associated with one pair of memory cells from the next, diffused areas 28 for forming the drain and source regions of transistors 46A and 46B, gate electrodes 30 that are each coupled to or form portions of a word line (extending orthogonal to the plane of FIG. 3 and therefore not shown), and isolation layers 32 and 34. Capacitors 48A and 48B are formed with a bottom electrode 36, typically fabricated of platinum and connected to a common "plate line" that is in turn coupled to a plurality of memory cells. The plate line is also orthogonal to the plane of FIG. 3 and therefore not shown. Capacitors 48A and 48B also include a ferroelectric dielectric layer 38 and a top electrode 40, also usually fabricated of platinum. The top electrodes 40 of the capacitors are coupled to respective source regions of transistors 46A and 46B via a metalization layer 42. Metalization layer 42 also contacts the common drain of transistors 46A and 46B, forming a common bit line contact. A passivation layer 44 of silicon dioxide (SiO.sub.2) is subsequently deposited over the entire surface of the integrated circuit.
The schematic diagram of FIG. 4A shows a memory cell 22' that roughly corresponds to the integrated ferroelectric memory cell 22 shown in the cross sectional diagram of FIG. 3, except that two distinct bit lines are shown instead of a single shared bit line contact. Memory cell 22' includes a word line 50 designated "WL", a plate line 52 designated "PL" and separate bit lines 54 and 56 designated BL and BL*, respectively. One portion of the memory cell 22' includes transistor 46A and ferroelectric capacitor 48A. Word line 50 is coupled to transistor 46A through gate contact 30, plate line 52 is coupled to ferroelectric capacitor 48A through bottom electrode 36, and bit line 54 is coupled to transistor 46A through one of the diffused areas 28. The other portion of memory cell 22' includes transistor 46B and ferroelectric capacitor 48B. Word line 50 is coupled to transistor 46B through gate contact 30, plate line 52 is coupled to ferroelectric capacitor 48B through bottom electrode 36, and bit line 54 is coupled to transistor 46B through one of the diffused areas 28.
Typically, in a two-transistor, two-capacitor ("2T-2C") memory cell having complementary bit lines, a valid logic state is resolved by comparing the two bit lines with a sense amplifier (not shown in FIG. 4A). Capacitors 48A and 48B are poled in opposite directions. When interrogated by pulsing the plate line 52, differing amounts of charge are transferred to the bit lines, depending upon the direction of the polarization vector in capacitors 48A and 48B.
The schematic diagram of FIG. 4B shows a 1T-1C ferroelectric memory cell 58. Memory cell 58 includes a word line 50, a plate line 52, a bit line 54 and a reference line 60 designated "REF." Word line 50 is coupled to the gate of transistor 46, plate line 52 is coupled to ferroelectric capacitor 48, and bit line 54 is coupled to a drain/source node of transistor 46. Typically, in a 1T-1C memory cell a valid logic state is resolved on bit line 54 by comparing the bit line charge and the reference charge on reference line 60 with a sense amplifier (not shown in FIG. 4B). When interrogated by pulsing the plate line 52, a charge is transferred to bit line 54 that is either less than or greater than the reference charge, so that a valid logic state can be resolved by the sense amplifier.
The operation of ferroelectric capacitors such as those found in the memory cells of FIG. 4A and FIG. 4B is described in further detail with reference to the hysteresis FIG. 160 shown in FIG. 6A and the corresponding voltage waveform shown in FIG. 6B. FIG. 6A is a plot of the voltage versus charge or polarization behavior of a ferroelectric capacitor. While reference may be made to "charge" in the dielectric of the ferroelectric capacitor, it should be noted that the capacitor charge dissipates, i.e. is volatile. However hysteresis curve 160 also represents polarization, which is non-volatile. Reference is made to both aspects of charge and polarization, which generally correspond before the charge on the ferroelectric capacitor dissipates. One characteristic of a ferroelectric material such as PZT is a hysteresis curve or loop 160 as shown in FIG. 6B, wherein the x-axis represents the field voltage applied to the material and the y-axis represents the polarization vector (or charge) of the ferroelectric material. The flow of current through a ferroelectric capacitor depends on the prior history of the applied voltages. A voltage waveform 168 is shown in FIG. 6B that includes two positive voltage pulses and two negative voltage pulses that are applied to one electrode of a ferroelectric capacitor in a Sawyer tower circuit arrangement, which is explained in further detail below with reference to FIG. 5. The exact timing of the pulses is arbitrary, and can include extremely long pulse widths. Circled point numbers one through six on hysteresis curve 160 of FIG. 6A correspond to the same circled point numbers on the voltage waveform 168 of FIG. 6B.
Turning momentarily to FIG. 5, a Sawyer tower circuit is shown having a ferroelectric capacitor 152 in series with a conventional, "linear" load capacitor 154. The size of load capacitor 154 is made large with respect to the size of ferroelectric capacitor 152 so that most of the input voltage, V.sub.IN, supplied by voltage waveform 150, is dropped across ferroelectric capacitor 152. The output voltage, V.sub.OUT, provided by the Sawyer tower circuit, generates the characteristic hysteresis curve 156 typical of ferroelectric materials such as PZT.
Referring again to FIG. 6A, starting at a first point 161 on both the hysteresis FIG. 160 and the voltage waveform of FIG. 6B (which also corresponds to circled point number one), there is no externally-applied voltage across the ferroelectric capacitor being characterized, but previously a voltage was applied across the ferroelectric capacitor that left the capacitor polarized at point 161. Applying a positive voltage across the ferroelectric capacitor moves the operating point (i.e., the current polarization) along the hysteresis curve 160 to a second point 162. The change in polarization vector or charge is designated "P" and is labeled on the rising edge of the first voltage pulse shown in the voltage waveform 168 of FIG. 6B and on the hysteresis curve 160 shown in FIG. 6A. The charge liberated with the change in polarization vector (in this case, traversing from point 161 to point 162) is referred to as the "switched charge." Next, the trailing edge of the first pulse in FIG. 6B occurs between circled numbers 2 and 3, or points 162 and 163 on hysteresis curve 160. This transition is typically caused by a return-to-zero transition in the externally applied voltage. Returning the externally-applied positive voltage pulse moves the polarization along the hysteresis curve 160 to a third point 163. The direction component of spontaneous remnant polarization within the ferroelectric capacitor is unchanged in the transition from point 162 to point 163, although there is some loss of field induced polarization, i.e. a loss in the polarization magnitude in a non-ideal ferroelectric material used in the capacitor dielectric. The change in charge is designated "P.sub.a " (which is read as "P after") and is labeled on the falling edge of the first voltage pulse shown in FIG. 6B and on the hysteresis curve 160 shown in FIG. 6A. Circled point 3 on waveform 168 represents a zero externally-applied voltage and, but note that while the horizontal (voltage) component of hysteresis curve 160 is zero at point 163, there is a non-zero vertical component. Ideally, this remnant polarization ought to remain indefinitely. However, in practice some "relaxation" may occur. This is shown in FIG. 6A as the transition between points 163 and 164. Specifically, between the third and fourth points 163 and 164 on the hysteresis curve 160, there is a reversal of the polarization vector in some portion of the domains within the ferroelectric capacitor, resulting in a partial loss of the overall polarization magnitude.
Applying a second positive voltage across the ferroelectric capacitor moves the operating point from the fourth point 164 on the curve 160 back to the second point 162. The increase in charge is now labeled "U" and is less than the P increase produced by the first positive voltage. Removing the applied positive voltage moves the operating point to the fifth point 165 on the hysteresis curve 160, with a corresponding loss of charge labeled "U.sub.a " (which is read as "U after").
Applying a negative voltage across the ferroelectric capacitor at the fifth point 165 on the hysteresis curve 160 moves the operating point to a sixth point 166. The change in charge and polarization is labeled "N" and is shown on the leading edge of the first negative pulse in FIG. 6B (circled point 6 of waveform 168). The negative voltage reverses the polarization direction of the capacitor, resulting in the original polarization direction. Since the hysteresis curve is substantially symmetrical, removing and reapplying the negative voltage moves the operating point around the "bottom" portion of the hysteresis curve 160 in the same manner as described above with reference to operating points 161 through 165. The associated changes in charge around the bottom of hysteresis loop 160 are consecutively labeled "N", "N.sub.a " (which is read as "N after), "D" and "D.sub.a " (which is read as "D after") on waveform 168 of FIG. 6B. Note that the relaxation of the loop is not shown in the bottom portion of hysteresis loop 160, though it exists in a non-ideal ferroelectric capacitor. For the sake of simplicity in FIG. 6A, the bottom charge components labeled "N.sub.a ", "D" and "D.sub.a " are assumed to all be approximately equal. After the two negative voltage pulses are applied and returned to zero applied volts, the operating point is returned to the first point 161 on the hysteresis curve 160.
The memory cells shown in FIGS. 4A and 4B have the ability to store non-volatile data since the polarization vector stored in the ferroelectric capacitors in the cells remains once the poling electric field has been removed. The ability to preserve data in a ferroelectric memory for a long period of time is generally known as "retention." Retention includes the ability to store and read the same data state (same state performance). Retention also includes the ability to store an initial data state for a long period of time, followed by writing an opposite data state and correctly reading that opposite data state (opposite state performance). While the same state performance of a ferroelectric memory is seldom at issue, the opposite state performance of a ferroelectric memory is frequently a cause for concern. The failure to correctly read the opposite data state is generally known as "imprint", and refers to the fact that the original data state has been imprinted in the memory.
It is desirable, therefore, that retention performance be maximized as much as possible, primarily by minimizing the imprint failure mechanism. It is known that either strontium (Sr) or calcium (Ca) used singly can be used to dope the A site of the unit cell 10 for various purposes such as influencing the dielectric properties of a ferroelectric material. It is also known that lanthanum (La) can be used to dope the A site of the unit cell 10 for improved endurance (ability to withstand loss of polarization due to cycling) of a ferroelectric memory. However, any improvement in retention performance attained by the prior art single species dopant method must be further improved to meet the ever increasing demands of the marketplace for quality non-volatile memory devices.
What is desired is a ferroelectric memory having maximum retention performance beyond that which is currently available.